This invention relates to semiconductor memory devices and more particularly, it relates to a VMOS-type integrated circuit random access memory device with improved performance characteristics and to a method for fabricating such devices.
In the development of semiconductor memory devices and for digital computers, a considerable effort has been made to increase the number of memory cells per unit area, improve reliability, speed, and to reduce operating power, and also provide a device with a large number of cells that can be manufactured with relatively high yield factors. One important step forward in the art that fulfilled the aforesaid objectives to a significant degree is disclosed in U.S. Pat. No. 4,003,036, which is assigned to the assignee of the present invention. In the aforesaid patent, a single VMOS transistor memory cell is provided in conjunction with a buried and isolated souce region formed within the substrate directly below a diffused bit line of the same conductivity type material. The VMOS transistor is formed by a V-shaped recess that extends through the diffused bit line and into the buried source region a word line together with that extends through the recess and forms an integral gate region therewith. One disadvantage with the aforesaid arrangement was that the VMOS drain overlap around the upper edge of the V-groove recess caused relatively larger bit line area, thereby increasing overall bit line capacitance while also requiring a relatively large cell. The present invention overcomes these problems while maintaining the basic inherent advantages of the V-groove and buried source combination in an integrated circuit semiconductor memory device.